Y Low power Schottky version of 2502 Y Storage and control for successive approximation A to
D conversion Y Performs serial-to-parallel conversion
Connection Diagram
Dua.
The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs syn.
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